Semiconductor memory devices comprise volatile and non-volatile types. A volatile memory device loses data stored in its memory cells when power is cut off. A non-volatile memory device does not lose data stored in the memory cells when power is cut off. DRAM and SRAM are volatile memory devices. A mask read only memory (Mask-ROM), an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), flash memories and the like are non-volatile memory devices. Most non-volatile memories can be erased and programmed.
The EEPROM can be either a flash memory device in a stack gate structure or a flash memory device in a split gate structure. The stack gate structure device comprises a floating gate and a control gate which are sequentially stacked. The floating gate stores electronic charges and the control gate controls switching operations. On the other hand, the split gate structure device includes a control gate which is disposed adjacent to one side of the floating gate.
FIGS. 1-4 are cross-section views showing steps of forming a flash memory device in a conventional split gate structure. Reference numbers “a” and “b” of the drawings represent a cell region and a peripheral circuit region, respectively.
Referring to FIG. 1, a tunnel insulating layer 2, a floating gate conductive layer 3 and a mold layer 4 are sequentially formed on an entire surface of a semiconductor substrate 1. The tunnel insulating layer 2 is formed of a thermal oxide layer and the floating gate conductive layer 3 is formed of a doped polysilicon layer. The mold layer 4 is formed of a silicon nitride layer. The mold layer 4 is patterned to form a groove 5 exposing a predetermined region of the floating gate conductive layer 3 of the cell region “a”. The floating gate conductive layer 3 exposed by the groove 5 is recessed to a predetermined thickness. Preliminary spacers 6 are formed on both sidewalls of the groove 5. The preliminary spacers 6 are formed of a silicon oxide layer. Using the preliminary spacers 6 and the mold layer 4 as an etching mask, the floating gate conductive layer 3 and the tunnel insulating layer 2 are successively etched to expose a predetermined region of the semiconductor substrate 1. Impurity ions are implanted into the exposed semiconductor substrate 1 to form a source region 7. A liner oxide layer (not shown) is formed on an entire surface of the semiconductor substrate 1 including the source region 7. The liner oxide layer is etched back until the mold layer 4 is exposed, thereby forming liner spacers 8 on the preliminary spacers 6. Spacers 9 comprise the preliminary spacers 6 and the liner spacers 8. A source conductive layer 10 is formed on an entire surface of a semiconductor substrate 1 including the spacers 9, thereby filling the groove 5. The source conductive layer 10 is formed of a doped polysilicon layer.
Referring to FIG. 2, the source conductive layer 10 is planarized until the mold layer 4 is exposed. Thus a source line 10a is formed in the groove 5. The exposed mold layer 4 and the floating gate conductive layer 3 under the mold layer 4 and the tunnel insulating layer 2 are successively etched to expose the semiconductor substrate 1. Thus, a floating gate electrode 3a is formed in the spacer 9. The semiconductor substrate 1 is exposed at the peripheral circuit region “b”.
A control gate insulating layer 21, a control gate conductive layer 22 and an oxidation barrier layer 23 are sequentially formed on an entire surface of the semiconductor substrate 1 including the floating gate electrode 3a. The control gate insulating layer 21 is made of a silicon oxide layer and the control gate conductive layer 22 is formed of a doped polysilicon layer. The oxidation barrier layer 23 is formed of a silicon nitride layer.
Referring to FIGS. 3 and 4, the oxidation barrier layer 23, the control gate conductive layer 22 and the control gate insulating layer 21 are planarized by a chemical mechanical polishing process, thereby exposing a top surface of the source line 10a. Therefore, an oxidation barrier pattern 23a is formed where a step coverage is low in the cell region “a”. The control gate conductive layer 22 that is located on the spacer 9 and the source line 10a is etched. Thus, a portion of the control gate conductive layer 22 is exposed between the spacer 9 and the oxidation barrier pattern 23a. 
An oxidation barrier pattern 23a having an identical step coverage with the oxidation barrier pattern 23a of the cell region “a” is formed at the peripheral circuit region “b”.
Hard mask layers 25 are formed on top surfaces of the control gate conductive layer 22 and the source line 10a that are exposed in the cell region “a”. Each of the hard mask layer 25 is formed of a thermal oxide layer.
Using the hard mask layer 25 as a mask, the oxidation barrier pattern 23a is etched to expose the control gate conductive layer 22 under the oxidation barrier pattern 23a. The control gate conductive layer 22 is anisotropically etched to form a control gate line 22a in the cell region “a” using the hard mask layer 25 of the cell region “a” as a mask. To prevent from being etched, the control gate conductive layer 22 of the peripheral circuit region “b” may be covered by the photo sensitive layer.
As explained above, a dishing phenomenon may occur during the chemical mechanical polishing process to expose a portion of the control gate conductive layer 22. The dishing results from a step coverage or a pattern density of the cell region “a” and the peripheral circuit region “b”. A reference number k represents an etching surface that may be etched by dishing. Because of dishing, the shape of the furthest peripheral cell m of the cell region “a” may be degraded. In addition, the control gate conductive layer 22, which extends from the furthest peripheral cell m to the peripheral circuit region “b” may be exposed. Therefore, the hard mask layer 25 may be formed on the exposed control gate conductive layer 22b. As a result, when the control gate line 22a is formed using the hardmask layer 25 as a mask, the control gate line 22a of the furthest peripheral cell m may not be formed.
A need therefore exists for a non-volatile memory device with minimal degradation of a furthest peripheral cell of a cell region due to dishing.